The present invention relates to a semiconductor device. More particularly, it relates to a semiconductor device having a storage device including a multilayer structure of metal materials.
As semiconductor devices such as semiconductor integrated circuits for storage, there have been conventionally used integrated circuits of storage elements each having a structure formed in a so-called column in which two or more layers each including a conductor are stacked such as a MRAM (Magnetic Random Access Memory), a ReRAM (Resistance Random Access Memory), and a PRAM (Phase change Random Access Memory). Out of these, the semiconductor devices using a MRAM are disclosed in, for example, Japanese Unexamined Patent Publication No. 2008-141210 (which will be hereinafter referred to as “Patent Document 1”) and Japanese Unexamined Patent Publication No. 2008-218649 (which will be hereinafter referred to as “Patent Document 2”). For the storage element, by the current flowing through a wire electrically coupled to a storage element called a bit line, the change in electrical resistance value can be read as data.
Incidentally, in the semiconductor device including the MRAMs or the like, there are disposed a memory cell region including a plurality of storage elements such as MRAMs disposed therein in a collected manner, and a peripheral region not including storage elements such as MRAMs disposed therein, disposed in the periphery of the memory cell region in plan view. In the peripheral region, storage elements are not formed. However, there may be disposed a region in which a layer equal or similar in material to that of the storage element is formed as a dummy. The semiconductor devices in each of which a dummy pattern is formed in the peripheral region are respectively disclosed in, for example, Japanese Unexamined Patent Publication No. 2010-93277 (which will be hereinafter referred to as “Patent Document 3”), Japanese Unexamined Patent Publication No. 2003-187570 (which will be hereinafter referred to as “Patent Document 4”), and Japanese Unexamined Patent Publication No. 2004-228187 (which will be hereinafter referred to as “Patent Document 5”).
[Patent Document 1]
    Japanese Unexamined Patent Publication No. 2008-141210[Patent Document 2]    Japanese Unexamined Patent Publication No. 2008-218649[Patent Document 3]    Japanese Unexamined Patent Publication No. 2010-93277[Patent Document 4]    Japanese Unexamined Patent Publication No. 2003-187570[Patent Document 5]    Japanese Unexamined Patent Publication No. 2004-228187